15
■ 32-bit/33-MHz cPCI system slot, 4 HP
■ MPC8540, 800MHz (PowerQUICC
™
III)
■ FPGA 12,000 LEs (approx. 144,000 gates)
■ Up to 2 GB DDR DRAM (SO-DIMM)
■ NAND Flash
■ 2 Gigabit/1 Fast Ethernet (RJ45 on front)
■ 1 COM (RJ45 on front)
■ FPGA for user-defined I/O functions
■ MENMON
™
BIOS for PowerPC
®
cards
F13 – 3U CompactPCI
®
MPC8540 SBC
CPU
■ PowerPC
®
■ MPC8540 PowerQUICC
™
III
■ 800MHz (666..833MHz optional)
■ e500 PowerPC
®
core with SPE APU and MMU
■ Integrated Northbridge and Southbridge
■ High memory bandwidth
Memory
■ 2x32KB L1 data and instruction cache,
256KB L2 cache/SRAM integrated in
MPC8540
■ Up to 2GB SDRAM system memory
■ One SO-DIMM slot for SDRAM modules
■ DDR2100 with or without ECC
■ 133MHz memory bus frequency
■ Up to 1GB soldered NAND Flash
(and more), FPGA-controlled
■Up to 16MB additional SDRAM, FPGA-contr.,
e.g. for video data and NAND Flash firmware
■ 8MB boot Flash
■ 32KB non-volatile FRAM
■ Up to 16MB additional SDRAM,
FPGA-controlled, e.g. for video data
■ Serial EEPROM 4kbits for factory settings
Mass Storage
■ Parallel IDE (PATA)
■ One IDE port via 44-pin on-board connector
■ FPGA-controlled
■ PIO mode 0 support
■Up to 1GB soldered ATA NAND Flash
(and more), FPGA-controlled
I/O
■ Three Ethernet channels
■ Two 10/100/1000Base-T Ethernet channels
■ One 10/100Base-T Ethernet channel
■ Three RJ45 connectors at front panel
■ Two on-board LEDs to signal LAN Link and
Activity
■ One RS232 UART (COM1)
■ One RJ45 connector at front panel
■ Data rates up to 115,2 kbits/s
■ 16-byte transmit/receive buffer
■ Handshake lines: CTS, RTS
■ One UART (COM10)
■ FPGA-controlled
■ Accessible via I/O connector
■ Physical interface at front panel using
SA-Adapter
™
via 10-pin ribbon cable on
I/O connector
■ RS232..RS485, isolated or not: for free use in
system (e. g. cable to front)
■ Data rates up to 115kbits/s
■ 16-byte transmit/receive buffer
■ Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
■ GPIO
■ 36 GPIO lines
■ FPGA-controlled
■ Connection via on-board I/O connector
■ Further I/O depending on
FPGA configuration
Front Connections (Standard)
■ Three Ethernet (RJ45)
■ One RS232 UART (RJ45)
FPGA
■ Standard factory FPGA configuration:
■ Main bus interface
■ 16Z070_IDEDISK – IDE controller
for NAND Flash
■ 16Z043_SDRAM – SDRAM contr. (16MB)
■ 16Z023_IDE_NHS –IDE controller
(PIO mode 0; non-hot-swap)
■ 16Z025_UART – UART controller
(controls COM10)
■ 16Z034_GPIO – GPIO controller
(40 lines, 5 IP cores)
■ The FPGA offers the possibility to add
customized I/O functionality. See website.
Miscellaneous
■ Real-time clock with GoldCap backup
■ Power supervision and watchdog
■ Reset button, GPIO-controlled
■ Three user LEDs, GPIO-controlled; 1 FPGA
power status LED
CompactPCI
®
Bus
■ Compliance with CompactPCI
®
Core
Specification PICMG 2.0 R3.0
■ System slot
■ 32-bit/33-MHz PCI-to-PCI bridge
■ V(I/O): +3.3V (+5V tolerant)
PXI™
■ Four trigger lines compliant with PXI
™
Specification R1.0
PowerPC®
MPC8540
SDRAM
Main
(SO-DIMM)
RTC /
Watchdog
EEPROM
FPGA
PCI
Bus
F
F
RS232 COM1
F
F
Boot
Flash
FRAM
Ethernet
10/100/1000Base-T
Ethernet
10/100/1000Base-T
Ethernet
10/100Base-T
SDRAM
Additional
NAND
Flash
PCI-104 P1
CompactPCI® J1/J2
PCI-to-PCI Bridge
Option: Busless
IDE
COM10
GPIO
B
B
F
SA
B
I/O Connector P2
I/O
F
B
Front Panel
On Board
MEN 3U CompactPCI and CompactPCI Express
PowerPC and Nios-based
(130 paginas)
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