16
CPU
■ PowerPC
®
■ MPC5200B
■ Up to 400MHz
Memory
■ 2x16KB L1 data and instruction cache
integrated in MPC5200
■ Up to 256MB SDRAM system memory
■ Soldered
■ DDR
■ 64MHz memory bus frequency
■ Up to 1GB soldered NAND Flash (and more),
FPGA-controlled
■ 16MB additional SDRAM, FPGA-controlled,
e.g. for video data and NAND Flash firmware
■ Up to 8MB boot Flash
■ 2MB GoldCap-backed SRAM, or: 128KB
non-volatile FRAM
■ Serial EEPROM 8kbits for factory settings
Mass Storage
■ Parallel IDE (PATA)
■ One IDE port via 44-pin on-board connector
■ FPGA-controlled
■ PIO mode 0 support
■ Up to 1GB soldered ATA NAND Flash
(and more), FPGA-controlled
I/O
■ USB
■ One USB 1.1 port
■ Series A connector at front panel
■ OHCI implementation
■ Data rates up to 12Mbits/s
■ Ethernet
■ Two 10/100Base-T Ethernet channels
■ One channel FPGA-controlled
■ Two RJ45 or one D-Sub conn. at front panel
■ One RS232 UART (COM1)
■RJ45 or D-Sub connector at front panel
■ Data rates up to 115.2kbits/s
■ 512-byte transmit/receive buffer
■ Handshake lines: CTS, RTS
■ One UART (COM10)
■ Accessible via I/O connector
■ Physical interface at front panel using
SA-Adapter™ via 10-pin ribbon cable on I/O
connector
■ RS232..RS485, isolated or not: for free use in
system (e. g. cable to front)
■ Data rates up to 115.2kbits/s
■ 16-byte transmit/receive buffer
■ Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
■ CAN bus
■ Two CAN bus channels
■ 2.0 A/B CAN protocol
■ Data rates up to 1 Mbit/s
■ Connection via on-board connectors
■ External transceivers using SA-Adapters™
■ GPIO
■ 36 GPIO lines; FPGA-controlled
■ Connection via on-board I/O connector
■ Further I/O depending on FPGA configuration
Front Connections (Standard)
■ One USB 1.1 (Series A)
■ Two Ethernet (RJ45)
■ One RS232 UART (RJ45)
FPGA
■ Standard factory FPGA configuration:
■ Main bus interface
■ 16Z070_IDEDISK - IDE contr. for NAND Flash
■ 16Z043_SDRAM - Additional SDRAM
controller (16MB)
■ 16Z023_IDENHS - IDE controller
(PIO mode 0; non-hot-swap)
■ 16Z087_ETH - Ethernet contr. (10/100Base-T)
■ 16Z025_UART - UART contr. (controls COM10)
■ 16Z034_GPIO - GPIO controller
(40 lines, 5 IP cores)
■ The FPGA offers the possibility to add
customized I/O functionality. See FPGA.
Miscellaneous
■ Real-time clock with GoldCap backup
■ Power supervision and watchdog
■ Reset button, GPIO-controlled
■ Three user LEDs, GPIO-controlled; 1 FPGA
power status LED
CompactPCI
®
Bus
■ Compliance with CompactPCI
®
Core
Specification PICMG 2.0 R3.0
■ System slot
■ 32-bit/32-MHz PCI-to-PCI bridge
■ V(I/O): +3.3V or +5V (Universal Board)
PXI™
■ Four trigger lines compliant with PXI™
Specification R1.0
■ 32-bit/33-MHz cPCI system slot, 4 HP
■ MPC5200B / 384 MHz
■ FPGA 18,752 LEs (approx. 225,000 gates)
■ Up to 256 MB on-board DDR SDRAM
■ Up to 8 MB boot Flash, NAND Flash
■ 2 MB SRAM, 16 MB graphics memory
■ Dual Fast Ethernet, COM, USB (front)
■ Dual CAN bus controller
■ FPGA for user-defined I/O functions
■ MENMON™ BIOS for PowerPC
®
cards
■ -40 to +85°C with qualified components
F12N – 3U CompactPCI
®
MPC5200B SBC
PowerPC and Nios-based
PowerPC®
MPC5200B
SDRAM
Main
SRAM/
FRAM
Ethernet
10/100Base-T
RTC
EEPROM
FPGA
SDRAM
Additional
RS232 COM1
Multifunction external bus
F
F
PCI-104 P1
Watchdog
CAN bus
Boot
Flash
B
USB 1.1 F
NAND
Flash
CAN bus B
Ethernet
10/100Base-T
F
F
SA
F
SA
CompactPCI® J1/J2
PCI-to-PCI Bridge
Option: Busless
IDE
COM10
GPIO
B
B
F
SA
B
I/O
I/O Connector P2
F
B
Front panel
On-board
MEN 3U CompactPCI and CompactPCI Express
(130 paginas)
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